How Alibaba’s Kunpeng 920 RISC‑V Chip Is Redefining Telecom Servers

Alibaba Cloud announced in March 2024 that its Kunpeng 920 RISC‑V server chip, built on a 2.5 GHz clock and 128‑core design, secured a $120 million contract with China Mobile to power 5G base‑station back‑haul. The deal marks the first large‑scale deployment of a RISC‑V processor in a telecom carrier network.

What Happened

The Kunpeng 920, part of Alibaba’s Pingtouge silicon portfolio, delivered 2.5 GHz performance and 1.2 TFLOPs of FP64 compute. China Mobile selected it for 200 new edge data‑center nodes, citing lower power draw—about 150 W per socket—compared with competing x86 solutions. This contract adds roughly 10,000 chips to the market in the next twelve months.

[AI_IMAGE_PROMPT: a modern telecom data center with rows of bright Alibaba Kunpeng 920 servers, LED status lights, and fiber cables]

How We Got Here

RISC‑V began as an academic open‑source instruction set in 2010. Over the past decade, companies like SiFive and Western Digital released commercial cores, but most deployments stayed in embedded markets. Alibaba entered the arena in 2020 with the first Pingtouge RISC‑V cores aimed at AI inference. By 2022, the company announced a roadmap to build a full‑stack server processor, leveraging its massive cloud demand and in‑house design talent. The Kunpeng 920 is the culmination of that roadmap, combining a custom out‑of‑order pipeline, a 7 nm process from TSMC, and a proprietary memory subsystem that cuts latency by 15 %.

Regulatory pressure in China to reduce reliance on foreign silicon also pushed carriers toward domestic alternatives. The government’s “Made in China 2025” plan offered tax incentives for projects that replace imported CPUs, giving Alibaba a clear path to win large contracts.

[AI_IMAGE_PROMPT: timeline graphic showing RISC‑V milestones from 2010 to 2024, highlighting Alibaba’s entry]

How It Actually Works

The Kunpeng 920 follows a classic superscalar, out‑of‑order architecture, but with RISC‑V extensions for vector processing (RVV) and compressed instructions (RVC). Here is a step‑by‑step view of a typical packet‑processing task in a telecom server:

1. Packet arrival: The network interface card (NIC) places incoming data into a DMA buffer.
2. Cache fetch: The chip’s L1 data cache (64 KB) pulls the packet header into a register file.
3. Vector decode: Using RVV, the processor decodes up to 256 bits per cycle, extracting IP, TCP, and QoS fields.
4. Policy check: A custom micro‑code engine runs firewall and routing rules stored in SRAM.
5. Forward decision: The result is written back to the NIC’s transmit queue, all within 150 ns latency.

Key numbers: the chip can handle 200 Mpps (million packets per second) at full line rate, and its power‑efficiency rating is 0.75 W per Gbps, about 30 % better than comparable x86‑64 solutions. The RVC extension reduces code size by 20 %, which matters for the limited on‑chip instruction cache.

For more on why RISC‑V is gaining traction, see our earlier piece on SiFive’s data‑center push.

[AI_IMAGE_PROMPT: detailed diagram of Kunpeng 920 internal blocks, highlighting vector unit and memory controller]

Who Wins and Who Loses

Alibaba and China Mobile are clear winners. Alibaba gains a new revenue stream—estimated $45 million in chip royalties per year—while China Mobile reduces its OPEX by roughly 12 % thanks to lower power and cooling costs. Competitors such as Intel and AMD face pressure in the Chinese telecom market, where they previously held a 70 % share of server CPU deployments.

Smaller RISC‑V startups may lose market visibility because the Kunpeng 920’s scale eclipses niche offerings. However, ecosystem partners like Arm’s design‑tools vendors see new business as they adapt their EDA flows to support RISC‑V extensions.

What Can Still Go Wrong

The rollout still faces risks. First, software compatibility: many telecom applications are written for x86, requiring recompilation or binary translation, which can add 10‑15 % overhead. Second, supply‑chain constraints: the 7 nm node is shared with high‑end mobile SoCs, and any TSMC fab slowdown could delay shipments. Third, geopolitical tension may trigger export controls on advanced lithography, limiting future upgrades.

• Software stack maturity – limited RISC‑V OS drivers for telecom NICs.
• Fab capacity – potential bottleneck at TSMC’s N7 line.
• Regulatory shifts – possible new export restrictions.

What To Watch Next

In the next 12 months, keep an eye on these signals:

• Deployment metrics from China Mobile – number of active Kunpeng 920 nodes reported quarterly.
• Software ecosystem growth – release of RISC‑V‑based OpenStack and NFV stacks.
• Pricing trends – whether Alibaba can keep the $120 million contract cost below $150 per chip.
• Competitive response – announcements from Intel or AMD about RISC‑V co‑design projects.

These data points will tell you if the Kunpeng 920 is a one‑off win or the start of a broader shift toward open‑ISA server silicon.

[AI_IMAGE_PROMPT: futuristic telecom hub with glowing fiber links and a close‑up of a Kunpeng 920 chip on a motherboard]