Google OpenTitan RISC‑V Security Chip Moves Toward Mass Production

Google announced that its OpenTitan root‑of‑trust (RoT) chip entered volume production on a 10 nm process in March 2026. The silicon, fabricated by TSMC, costs roughly $0.30 per die and ships to both Google data‑center racks and third‑party IoT makers. This milestone moves OpenTitan from prototype to a commercial security component.

What Happened

In March 2026, Google’s OpenTitan team confirmed that the first 10 nm batch of OpenTitan chips was taped‑out and received from TSMC. The production run includes 5 million dies, each featuring a RISC‑V‑C core, a hardware random number generator, and a secure boot ROM. The company posted a press release linking to the open‑source repository and promised that the chips would be available to any customer who can meet the licensing terms.

The announcement also highlighted that the chip supports a 1 Gbps secure channel for firmware updates, a feature that Google says will cut update latency by 40 % compared with legacy TPMs. For more background on Google’s earlier OpenTitan work, see the SiFive POC‑AI chip article.

[AI_IMAGE_PROMPT: a high‑tech lab with a glass enclosure showing a 10 nm silicon wafer, engineers in white suits, a holographic overlay of the OpenTitan block diagram]

How We Got Here

OpenTitan began in 2019 as a joint effort between Google, the Linux Foundation, and several silicon startups. The goal was to create a transparent, open‑source RoT that could replace proprietary TPMs and secure elements. Early prototypes ran on a 28 nm process and were used only in internal Google servers.

In 2022, the project released its first open‑source hardware description files on GitHub, inviting community contributions. By 2024, a handful of startups – including SiFive and GigaDevice – had built custom boards around the OpenTitan IP. However, the lack of a high‑density manufacturing partner kept costs high and limited adoption.

Google’s decision to partner with TSMC for a 10 nm node came after a two‑year evaluation of yield, power, and security metrics. The move mirrors the industry trend of shrinking RoT silicon to match mainstream processors, allowing the chip to sit on the same die or package as a main CPU without adding significant board space.

[AI_IMAGE_PROMPT: timeline graphic showing OpenTitan milestones from 2019 to 2026, with icons for each major release]

How It Actually Works

The OpenTitan chip is built around a small, in‑order RISC‑V‑C core that executes trusted firmware. It includes three main security blocks: a hardware random number generator (HRNG), a secure boot ROM, and a cryptographic accelerator. The HRNG draws entropy from ring‑oscillator jitter and feeds a SHA‑256 conditioner to produce high‑quality random bits.

During power‑on, the secure boot ROM verifies a signed firmware image stored in on‑chip flash. If the signature checks out, the core jumps to the firmware entry point; otherwise, the chip locks and signals an error over the 1 Gbps secure channel. Firmware can later request cryptographic services – such as AES‑256 encryption or ECDSA signing – from the accelerator, which runs in constant‑time to prevent side‑channel leaks.

Below is a step‑by‑step flow of a typical secure boot sequence:

1. Power is applied; the HRNG starts collecting entropy.
2. The boot ROM reads the firmware header from flash.
3. The header’s RSA‑2048 signature is verified using the public key baked into the ROM.
4. On success, the ROM copies the firmware to SRAM and jumps to its start address.
5. If verification fails, the chip sends an alert over the secure channel and halts.

All registers and memory regions are locked after boot, preventing any unauthorized reads. The chip also supports a “debug lock” mode that disables JTAG access unless a special unlock token is presented. For a deeper dive into the RISC‑V instruction set used, see the RISC‑V Wikipedia page.

[AI_IMAGE_PROMPT: schematic diagram of OpenTitan block diagram with labeled HRNG, boot ROM, crypto accelerator, and secure channel]

Who Wins and Who Loses

Data‑center operators stand to save up to 15 % on security‑related licensing fees by swapping proprietary TPMs for OpenTitan. Google estimates that each server can host up to eight OpenTitan chips, providing per‑core isolation for confidential workloads. The lower per‑die cost also benefits IoT manufacturers, who can now add hardware‑rooted security for less than $0.50 per device.

Companies that sell closed‑source secure elements – such as Infineon and Nuvoton – may see reduced market share in low‑margin segments. Their products typically cost $1–$2 per unit, so price‑sensitive customers will likely migrate to the open‑source alternative.

On the other hand, the open‑source community gains a high‑profile reference design that can be forked for custom needs. Startups can accelerate time‑to‑market by re‑using the verified OpenTitan IP instead of building a RoT from scratch.

[AI_IMAGE_PROMPT: bar chart comparing cost per unit of OpenTitan vs. traditional TPMs across data‑center and IoT markets]

What Can Still Go Wrong

Even with a mature silicon process, OpenTitan faces several risks. First, the open‑source model relies on rapid vulnerability disclosure and patching; a delayed firmware update could expose many devices at once. Second, the 10 nm node, while cost‑effective, still has a higher defect density than older nodes, which could affect yield and drive up prices if TSMC encounters capacity constraints.

Privacy advocates also warn that a widely deployed open RoT could become a target for nation‑state actors seeking to insert backdoors. Finally, the licensing terms require that any derivative firmware be released under the same open license, which may deter some commercial players.

• Potential firmware bugs that bypass secure boot.
• Supply‑chain disruptions at TSMC.
• Legal friction over open‑source licensing in proprietary products.

For a balanced view, read the recent TechCrunch analysis of open‑source hardware security here.

[AI_IMAGE_PROMPT: illustration of a supply‑chain map showing silicon wafer flow from TSMC to data‑center OEMs and IoT factories]

What To Watch Next

Over the next 12 months, keep an eye on these signals:

• Adoption rates reported by Google Cloud – a target of 20 % of new servers using OpenTitan by Q4 2027.
• First‑generation firmware patches that address any side‑channel findings.
• Announcements from other silicon vendors (e.g., SiFive, Andes) about porting OpenTitan to 7 nm or 5 nm processes.
• Regulatory guidance on open‑source RoT usage in critical infrastructure, especially in the EU’s Cybersecurity Act updates.

If these trends hold, OpenTitan could become the de‑facto standard for hardware‑rooted security across both cloud and edge ecosystems, reshaping how you design secure products.