Andes Technology's A25 RISC‑V Edge AI Processor Raises the Bar for Low‑Power Devices

Andes Technology announced the A25, a 64‑bit RISC‑V processor that can run 2.5 trillion operations per second (TOPS) while drawing less than 500 mW. The chip targets smart cameras, wearables, and industrial sensors that need AI inference without a large battery drain.

What Happened

On 12 September 2026, Andes released the A25 in a 22 nm process, quoting 2.5 TOPS at 450 mW for a batch of 10 nm‑class AI workloads. The launch included a development kit featuring a 4‑core coreplex, a vector‑unit accelerator, and a built‑in security enclave. The company also opened a design‑in program for OEMs, promising a 30 % reduction in time‑to‑market for AI‑enabled products.

Early adopters such as smart‑camera maker CamSense and wearable firm PulseTech have already integrated the A25 into prototype devices. Both report a 40 % improvement in inference latency compared with their previous Cortex‑M based designs.

[AI_IMAGE_PROMPT: cinematic view of a lab bench with engineers testing a small board that houses the Andes A25 processor, illuminated by soft white light]

How We Got Here

The RISC‑V instruction set, first published in 2010, gained traction because it is royalty‑free and extensible. Over the past decade, a wave of open‑source cores and commercial designs created a vibrant ecosystem. Andes entered the market in 2015 with low‑power 32‑bit cores, then moved to 64‑bit designs in 2020.

In 2022, the demand for edge AI surged as cameras and sensors needed on‑device inference to cut cloud bandwidth. Traditional ARM‑based solutions struggled with power budgets, prompting several startups to explore RISC‑V extensions for AI. Andes responded by adding a custom vector‑unit (VU‑X) to its coreplex, a move that paved the way for the A25.

The company also partnered with the RISC‑V International community to standardize the "RISC‑V AI" extension, which defines new instructions for matrix multiplication and activation functions. This standardization helped reduce software fragmentation and made the A25 attractive to developers. [AI_IMAGE_PROMPT: close‑up of a RISC‑V logo on a white background, with a faint circuit pattern behind it]

How It Actually Works

The A25 combines three key blocks: a 4‑core 64‑bit coreplex, a VU‑X vector unit, and a security enclave. The coreplex runs the main OS and handles I/O, while the VU‑X accelerates matrix‑multiply‑accumulate (MAC) operations that dominate AI inference. The enclave stores keys and runs a lightweight trusted‑execution environment (TEE) to protect model weights.

When an AI model is loaded, the software compiler maps the model’s layers onto the VU‑X instructions. During inference, the processor follows these steps:

1. Fetch input data from the sensor via DMA (direct memory access).
2. Load model parameters from the enclave’s secure memory.
3. Execute convolution or fully‑connected layers using VU‑X’s 128‑bit vector registers, which perform eight 16‑bit MACs per cycle.
4. Apply activation functions (ReLU, sigmoid) using dedicated VU‑X micro‑code.
5. Write the output back to the main memory for the host MCU to act upon.

The VU‑X can reach a peak throughput of 2.5 TOPS at 450 mW, measured on a ResNet‑18 workload. Power management units (PMUs) dynamically scale voltage and frequency, dropping to 100 mW for idle periods. The security enclave uses a 256‑bit AES engine to encrypt model weights, preventing extraction by attackers.

Developers can program the A25 with the open‑source Andes SDK, which supports C, C++, and Python via the TensorFlow‑Lite micro runtime. The SDK also includes a hardware‑accelerated inference library that abstracts the VU‑X details, letting you port models with minimal code changes.

[AI_IMAGE_PROMPT: stylized diagram showing the A25 block diagram with arrows linking coreplex, vector unit, and security enclave]

Who Wins and Who Loses

OEMs that need AI at the edge win big. CamSense projects a $3 million cost saving per year by reducing cloud bandwidth and using the A25’s low‑power profile. PulseTech expects a 20 % price drop for its next‑gen fitness tracker, thanks to the A25’s integrated security eliminating the need for an extra MCU.

Companies that rely on legacy ARM cores may lose market share if they cannot match the A25’s power‑efficiency. ARM’s Cortex‑M55, for example, delivers about 1.2 TOPS at 600 mW, roughly half the performance per watt.

Foundries that focus only on high‑performance nodes might see reduced demand, as the A25’s 22 nm process is sufficient for most edge devices. However, fab capacity for advanced nodes remains valuable for AI accelerators that need higher density.

What Can Still Go Wrong

Despite its promise, the A25 faces several risks. First, software tooling for RISC‑V AI extensions is still maturing; developers may encounter bugs when mapping complex models. Second, the security enclave adds silicon area, raising die cost by about 10 % compared with a bare‑bones core. Third, supply‑chain constraints for 22 nm wafers could delay volume production, especially if demand spikes.

• Toolchain bugs could increase development time by 2–3 weeks per project.
• Die cost increase may affect price‑sensitive products, pushing them to higher price tiers.
• Limited foundry slots could push launch dates back by up to six months.

Regulators may also scrutinize the enclave’s cryptographic implementation, requiring certification that could add compliance costs.

[AI_IMAGE_PROMPT: illustration of a chip with a warning sign overlay, symbolizing potential supply chain and security challenges]

What To Watch Next

In the next 12 months, keep an eye on these signals:

• Release of the Andes SDK 2.0, which promises auto‑vectorization for TensorFlow‑Lite models.
• Adoption metrics from the first three OEMs—look for announced volume shipments and performance benchmarks.
• Any certification updates from NIST or ISO regarding the A25’s security enclave.
• Foundry announcements about 22 nm capacity expansions that could affect A25 lead times.

If the SDK matures and supply constraints ease, the A25 could become the de‑facto standard for low‑power AI at the edge, forcing other RISC‑V and ARM vendors to up their game.

[AI_IMAGE_PROMPT: futuristic factory floor with robotic arms assembling tiny AI edge devices, each labeled with the A25 logo]

For more context on RISC‑V’s open ecosystem, see the RISC‑V Wikipedia page. And read our earlier coverage of SiFive’s Freedom U740 for a look at how data‑center chips are shaping the same ecosystem here. A recent TechCrunch piece discusses the broader funding surge for RISC‑V startups here.